1. Field of the Invention
The present invention generally relates to a method of forming a circuit pattern. More particularly, the present invention relates to a method of forming a circuit pattern with high aspect ratio by using supporting circuit lines or isolation structures.
2. Description of the Prior Art
High aspect ratio (AR) silicon trench etching is a key process to manufacture trench capacitor DRAMs. The capacitance is directly proportional to the surface of the capacitor. The size reduction in the next technologies requires the capacitance to be kept at similar values while the corresponding critical dimensions (CDs) are reduced. To ensure a sufficient capacitance, the aspect ratio of the trenches has to be increased.
Many methods, such as reactive ion etching (RIE), have been proposed to manufacture the silicon trenches with significantly high aspect ratios. Trench structures with aspect ratio higher than 30, even 40 or 50 may be easily obtain with these methods. However, in the application of forming line structures, such as bit lines or word lines in DRAMs, line structures are vulnerable to the bending or collapse issue when the aspect ratio of the line structure is too large. These issues may be easily found in line structures that are subject to other following process, such as thermal oxidation process. The bending or collapse of the line structures may severely impact the electrical performances of the memory device. Conventional etching processes, such as the above-mentioned RIE process, can only form high AR line structures. They cannot prevent the bending or collapse issues during the process of forming high AR line structures.
Accordingly, it is still necessary to provide a novel method for forming the structures, especially islands or line patterns, with high or ultra-high aspect ratio.